Publications for Erik Larsson
Co-author map based on ISI articles 2007-
Journal Articles
Breeta Sengupta, Urban Ingelsson and Erik Larsson
Scheduling Tests for 3D Stacked Chips under Power Constraints
Journal of electronic testing, 2012, 28(1), 121-135.
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Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson
Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
IEEE Design & Test Magazine, 2012, 29(2), 79-88.
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Erik Larsson and Einar Aas
European Test Symposium (ETS) 2011
Elektronikk - tidsskrift for IT och telekom, 2011, (4), 33-33.
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Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty and Zebo Peng
Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(5), 973-977.
Web of Science® Times Cited: 8 |
Erik Larsson and Zebo Peng
A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
Journal of electronic testing, 2008, 24(5), 497-504.
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Erik Larsson
An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
IET Computers and digital techniques, 2008, 2(4), 275-284.
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Erik Larsson and Stina Edbom
Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint
IET Computers and digital techniques, 2007, 1(1), 27-37.
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Erik Larsson and H Fujiwara
System-on-chip test scheduling with reconfigurable core wrappers
IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2006, 14(3), 305-309.
Web of Science® Times Cited: 15 |
Erik Larsson and Zebo Peng
Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process
I.E.E.E. transactions on computers (Print), 2006, 55(2), 227-239.
Web of Science® Times Cited: 8 |
Erik Larsson, Julien Pouget and Zebo Peng
Multiple Constraints Driven System-on-Chip Test Time Optimization
Journal of electronic testing, 2005, 21(6), 599-611.
Web of Science® Times Cited: 11 |
Erik Larsson, Julien Pouget and Zebo Peng
Abort-on-Fail Based Test Scheduling
Journal of electronic testing, 2005, 21(6), 651-658.
Web of Science® Times Cited: 2 |
Erik Larsson
Preemptive system-on-chip test scheduling
IEICE transactions on information and systems, 2004, E87D(3), 620-629.
Web of Science® Times Cited: 1 |
Erik Larsson, Klas Arvidsson, H Fujiwara and Zebo Peng
Efficient test solutions for core-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004, 23(5), 758-775.
Web of Science® Times Cited: 34 |
Erik Larsson and Zebo Peng
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Journal of electronic testing, 2002, 18(4-5), 385-400.
Web of Science® Times Cited: 51 |
Books
Chapters in Books
Anders Larsson, Urban Ingelsson, Erik Larsson and Krishnendu Chakrabarty
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
Design and Test Technology for Dependable Systems-on-chip, Information Science Publishing, 2010, .
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Dimitar Nikolov, Mikael Väyrynen, Urban Ingelsson, Erik Larsson and Virendra Singh
Optimizing Fault Tolerance for Multi-Processor System-on-Chip
Design and Test Technology for Dependable Systems-on-chip, Information Science Publishing, 2010, 578.
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Erik Larsson and C.P. Ravikumar
Power-Aware System-Level DfT and Test Planning
Power-Aware Testing and Test Strategies for Low Power Devices, Springer, 2009, .
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Erik Larsson and Zebo Peng
An Integrated System-on-Chip Test Framework
Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE, Springer, 2008, 439-454.
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Erik Larsson and Stina Edbom
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
Vlsi-Soc: From Systems To Silicon, Springer, 2007, 221-244.
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Erik Larsson and Zebo Peng
An Integrated Framework for the Design and Optimization of SOC Test Solutions
SOC (System-on-a-Chip) Testing for Plug and Play Test Automation., Kluwer Academic Publishers, 2002, 21-36.
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Conference Articles
Kim Petersen, Dimitar Nikolov, Urban Ingelsson, Gunnar Carlsson and Erik Larsson
An MPSoCs Demonstrator for Fault Injection and Fault Handling in an IEEE P1687 Environment
IEEE 17th European Test Symposimu (ETS 2012), Annecy, France, May 28-June 1, 2012, 2012.
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Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
VLSI 2012, 2012.
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Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Planning for Core-based 3D Stacked ICs under Power Constraints
RASDAT 2012, 2012.
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Dimitar Nikolov, Urban Ingelsson, Virendra Singh and Erik Larsson
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
5th Workshop on Dependable and Secure Nanocomputing (WSDN 2011), Hong Kong, June 27, 2011, 2011.
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Dimitar Nikolov, Urban Ingelsson, Virendra Singh and Erik Larsson
Study on the Level of Confidence for Roll-back Recovery with Checkpointing
1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011), Trondheim, Norway, May 26-27, 2011, 2011.
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Farrokh Ghani Zadegan, Urban Ingelsson, Erik Larsson and Gunnar Carlsson
A Study of Instrument Reuse and Retargeting in P1687
<em>IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011), MNIT Jaipur, India, November 25-26, 2011.</em>, 2011.
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Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Planning for 3D Stacked ICs with Through-Silicon Vias
3D-TEST, 2011.
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Urban Ingelsson, Shih-Yen Chang and Erik Larsson
Measurement Point Selection for In-Operation Wear-Out Monitoring
14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11), Cottbus, Germany, April 13-15, 2011., 2011.
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Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Scheduling for 3D Stacked ICs under Power Constraints
2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011, 2011.
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Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson
Design Automation for IEEE P1687
Design, Automation and Test in Europe (DATE 2011), Grenoble, France., 2011.
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Breeta SenGupta, Urban Ingelsson and Erik Larsson
Scheduling Tests for 3D Stacked Chips under Power Constraints
Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011, Queenstown, NZ, 2011.
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Erik Larsson, Farrokh Ghani Zadegan, Urban Ingelsson and Gunnar Carlsson
Test scheduling on IJTAG
Nordic Test Forum (NTF 2010), Drammen, Norway., 2010.
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Breeta SenGupta, Urban Ingelsson and Erik Larsson
Power Constrained Test Scheduling for 3D Stacked Chips: (poster)
<em>1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA.</em>, 2010.
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Dimitar Nikolov, Urban Ingelsson, Virendra Singh and Erik Larsson
Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
<em>5th IEEE Intl. Symposium on Electronic Design, Test & Applications (DELTA 2010), Ho Chi Minh City, Vietnam, January 13-15, 2010.</em>, 2010.
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Dimitar Nikolov, Urban Ingelsson, Virendra Singh and Erik Larsson
On-line Techniques to Adjust and Optimize Checkpointing Frequency
<em>IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010), Bangalore, India, January 7-8, 2010</em>, 2010.
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Jaynarayan T. Tudu, Erik Larsson, Virendra Singh and Hideo Fujiwara
Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
<em>Great Lakes Symposium on VLSI (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010.</em>, 2010.
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Jaynarayan T. Tudu, Erik Larsson, Virendra Singh and Hideo Fujiwara
Scan Cells Reordering to Minimize Peak Power During Test Cycle: A Graph Theoretic Approach
<em>IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010.</em>, 2010.
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Erik Larsson, Bart Vermeulen and Kees Goossens
A Distributed Architecture to Check Global Properties for Post-Silicon Debug
<em>IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010.</em>, 2010.
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Pramod Subramanyan, Virendra Singh, Kewal K. Saluja and Erik Larsson
Energy-Efficient Redundant Execution for Chip Multiprocessors
<em>Great Lakes Symposium on VLSI on (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010.</em>, 2010.
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Pramod Subramanyan, Virendra Singh, Kewal K. Saluja and Erik Larsson
Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
<em>The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10), Fairmont Chicago, Millennium Park, Chicago, Illinois, USA, June 28-July 1, 2010.</em>, 2010.
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Erik Larsson, Bart Vermeulen and Kees Goossens
Checking Pipelined Distributed and Global Properties at Post-silicon Debug
<em>DAC Workshop on Diagnostic Services in Network-on-Chips (DSNoC'10) , Anaheim, CA, USA, June 13-18, 2010.</em>, 2010.
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Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Singh and Erik Larsson
Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
<em>Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)</em>, 2010.
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Breeta SenGupta, Urban Ingelsson and Erik Larsson
Scheduling Tests for Stacked 3D Chips under Power Constraints
<em>Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)</em>, 2010.
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Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson and Erik Larsson
Efficient Embedding of Deterministic Test Data
<em>Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)</em>, 2010.
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Erik Larsson, Bart Vermeulen and Kees Goossens
Checking Pipelined Distributed Global Properties for Post-silicon Debug
<em>Workshop on RTL ATPG & DFT (WRTLT10), Shanghai, China, December 2010.</em>, 2010.
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Jaynarayan T. Tudu, Erik Larsson and Virendra Singh
Test Scheduling of Modular System-on-Chip under Capture Power Constraint
<em>Workshop on RTL ATPG & DFT (WRTLT10), Shanghai, China, December 2010.</em>, 2010.
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Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson and Erik Larsson
Efficient Embedding of Deterministic Test Data
<em>19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.</em>, 2010.
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N.S. Vinay, Indira Rawat, M.S. Gaur, Erik Larsson and Virendra Singh
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
<em>IEEE East-West Design & Test Symposium (EWDTS10), St. Petersburg, Russia, September 17-20, 2010.</em>, 2010.
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Pramod Subramanyan, Virendra Singh, Kewal K. Saluja and Erik Larsson
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
<em>Design Automation and Test in Europe (DATE), Dresden, Germany, March 8-12, 2010</em>, 2010.
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Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson
Test Time Analysis for IEEE P1687
<em>19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.</em>, 2010.
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Mikael Väyrynen, Virendra Singh and Erik Larsson
Fault-Tolerant Average Execution Time Optimization for System-On-Chips
<em>Frontiers of High Performance Embedded Computing, Bangalore, India, January, 2009.</em>, 2009.
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N.S. Vinay, Erik Larsson and Virendra Singh
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
<em>DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 20-24, 2009.</em>, 2009.
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Jaynarayan T. Tudu, Erik Larsson, Virendra Singh and Vishwani Agrawal
On Minimization of Peak Power for Scan Circuit during Test
<em>European Test Symposium (ETS 2009), Sevilla, Spain, May 25-29, 2009.</em>, 2009.
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Jaynarayan T. Tudu, Erik Larsson, Virendra Singh and Adit Singh
Capture Power Reduction for Modular System-on-Chip Test
<em>IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, July 8-10, 2009.</em>, 2009.
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Dan Adolfsson, Joanna Siew, Erik Larsson and Erik Jan Marinissen
Deterministic Scan-Chain Diagnosis for Intermittent Faults
<em>European Test Symposium (ETS 2009), Sevilla, Spain, May 25-29, 2009 (Poster).</em>, 2009.
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Pramod Subramanyan, Virendra Singh, Kewal K. Saluja and Erik Larsson
Power Efficient Redundant Execution for Chip Multiprocessors
<em>Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June 29, 2009.</em>, 2009.
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Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan T. Tudu, Erik Larsson and Virendra Singh
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
<em>7th IEEE East-West Design & Test Symposium (EWDTS), Moscow, Russia, September 18-21, 2009.</em>, 2009.
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Dan Adolfsson, Joanna Siew, Erik Jan Marinissen and Erik Larsson
On Scan Chain Diagnosis for Intermittent Faults
<em>IEEE Asian Test Symposium (ATS), Taichung, Taiwan, November 23-26, 2009.</em>, 2009.
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Venkat Rajesh, Erik Larsson, Manoj S. Gaur and Virendra Singh
An Even-Odd DFD Technique for Scan Chain Diagnosis
<em>Workshop on RTL and High Level Testing (WRTLT), Hongkong, China, November 27-28, 2009.</em>, 2009.
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Jaynarayan T. Tudu, Erik Larsson, Virendra Singh and Hideo Fujiwara
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
<em>10th IEEE Workshop on RTL and High Level Testing (WRTLT'09), </em><em>Hongkong, China, November 27-28, 2009.</em>, 2009.
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M. Vayrynen, V. Singh and Erik Larsson
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips
<em>Design Automation and Test in Europe (DATE 2009), Nice, France, April 20-24, 2009</em>, 2009.
Web of Science® Times Cited: 1 Fulltext
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Virendra Singh and Erik Larsson
On Reduction of Capture Power for Modular System-on-Chip Test
IEEE Workshop on RTL and High Level Testing WRTLT08,2008, 2008.
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Anders Larsson, Xin Zhang, Erik Larsson and Krishnendu Chakrabarty
SOC Test Optimization with Compression-Technique Selection
A Workshop in Conjunction with the International Test Conference,2008, 2008.
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Michael Söderman and Erik Larsson
Test Response Compression for Diagnosis in Volume Production
DAC08 Workshop on Diagnostic Services in Network-on-Chips DSNOC,2008, 2008.
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Anders Larsson, Xin Zhang, Erik Larsson and Krishnendu Chakrabarty
Core-Level Expansion of Compressed Test Patterns
17th Asian Test Symposium ATS,2008, 2008.
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Anders Larsson, Erik Larsson, Krishnendu Chakrabarty, Petru Ion Eles and Zebo Peng
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Design, Automation, and Test in Europe DATE 2008,2008, 2008.
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Erik Larsson, Gunnar Carlsson and Johan Holmqvist
Protocol Requirements in an SJTAG/IJTAG Environment
Nordic Test Forum NTF,2007, 2007.
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Erik Jan Marinissen, Dan Adolfsson, Erik Larsson and Sandeep-Kumar Goel
Improved Scan Chain Diagnosis
15th NXP IC Test Symposium,2007, 2007.
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Tobias Dubois, Erik Jan Marinissen, Mohamed Azimane, Paul Wielage, Erik Larsson and Clemens Wouters
Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07, 2007.
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Anders Larsson, Erik Larsson, Petru Ion Eles and Zebo Peng
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems,2007, 2007.
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Johan Holmqvist, Gunnar Carlsson and Erik Larsson
Extended STAPL as SJTAG Engine
IEEE European Test Symposium,2007, 2007.
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Erik Larsson, Mehdi Amirijoo, Daniel Karlsson and Petru Ion Eles
What Impacts Course Evaluation?
12th SIGCSE Conf. on Innovation and Technology in Computer Science Education,2007, 2007.
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Gunnar Carlsson, Johan Holmqvist and Erik Larsson
Protocol requirements in an SJTAG/IJTAG environment
IEEE International Test Conference, 2007, 2007.
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Anders Larsson, Erik Larsson, Petru Ion Eles and Zebo Peng
Optimized Integration of Test Compression and Sharing for SOC Testing
Design, Automation, and Test in Europe Conference DATE07,2007, 2007.
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Erik Larsson and Jon Persson
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
Asia and South Pacific Design Automation Conference,2007, 2007.
Web of Science® Times Cited: 4
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Erik Larsson
Combined Test Data Compression and Abort-on-Fail Test
24th IEEE Norchip Conference,2006, 2006.
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Soheil Samii, Erik Larsson, Krishnendu Chakrabarty and Zebo Peng
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
International Test Conference,2006, 2006.
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Tobias Dubois, Mohamed Azimane, Erik Larsson, Erik Jan Marinissen, Paul Wielage and Clemens Wouters
High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO
14th Philips Research IC Test Seminar,2006, 2006.
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Anders Larsson, Erik Larsson, Petru Ion Eles and Zebo Peng
SOC Test Scheduling with Test Set Sharing and Broadcasting
IEEE Asian Test Symposium,2005, 2005.
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David Bäckström, Gunnar Carlsson and Erik Larsson
Remote Boundary-Scan System Test Control for the ATCA Standard
International Test Conference ITC05,2005, 2005.
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Erik Larsson and Stina Edbom
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005},2005, 2005.
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Erik Larsson and Irtiyaz Gilani
A Test Data Compression Architecture with Abort-on Fail Capability
IEEE Workshop on RTL and High Level Testing WRTLT,2005, 2005.
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Anders Larsson, Erik Larsson, Petru Ion Eles and Zebo Peng
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
8th Euromicro Conference on Digital System Design DSD2005,2005, 2005.
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David Bäckström, Gunnar Carlsson and Erik Larsson
Boundary-Scan Test Control in the ATCA Standard
EEE European Board Test Workshop,2005, 2005.
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Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson and Erik Jan Marinissen
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
IEEE European Test Symposium ETS 05,2005, 2005.
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Erik Larsson, Julien Pouget and Zebo Peng
Defect-Aware SOC Test Scheduling
2004 IEEE VLSI Test Symposium VTS04,2004, 2004.
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Erik Larsson
Integrating Core Selection in the SOC Test Solution Design-Flow
International Test conference ITC04,2004, 2004.
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Anders Larsson, Erik Larsson, Petru Ion Eles and Zebo Peng
A Technique for Optimization of System-on-Chip Test Data Transportation
9th IEEE European Test Symposium,2004, 2004.
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Erik Larsson and Anders Larsson
Student-oriented Examination in a Computer Architecture Course
9th Annual Conference on Innovation and Technology in Computer Science Education,2004, 2004.
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Stina Edbom and Erik Larsson
An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
2004 IEEE Asian Test Symposium ATS 2004,2004, 2004.
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Erik Larsson, Julien Pouget and Zebo Peng
Defect Probability-based System-On-Chip Test Scheduling
6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems DDECS03,2003, 2003.
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Erik Larsson and Hideo Fujiwara
Test Resource Partitioning and Optimization for SOC Designs
2003 IEEE VLSI Test Symposium VTS03,2003, 2003.
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Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes and Bruno Rouzeyre
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
IEEE European Test Workshop 2003 ETW03,2003, 2003.
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Erik Larsson and Zebo Peng
A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling
International Test Conference ITC 2003,2003, 2003.
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Anders Larsson, Erik Larsson, Petru Ion Eles and Zebo Peng
Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03,2003, 2003.
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Erik Larsson and Hideo Fujiwara
Optimal System-on-Chip Test Scheduling
12th IEEE Asian Test Symposium ATS03,2003, 2003.
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Julien Pouget, Erik Larsson and Zebo Peng
SOC Test Time Minimization Under Multiple Constraints
12th IEEE Asian Test Symposium ATS03,2003, 2003.
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Erik Larsson and Hideo Fujiwara
Power Constrained Preemptive TAM Scheduling
7th IEEE European Test Workshop,2002, 2002.
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Erik Larsson, Klas Arvidsson, Hideo Fujiwara and Zebo Peng
Integrated Test Scheduling, Test Parallelization and TAM Design
IEEE Asian Test Symposium ATS02,2002, 2002.
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Erik Larsson and Zebo Peng
An Integrated System-On-Chip Test Framework
Design, Automation and Test in Europe DATE Conference,2001, 2001.
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Erik Larsson and Zebo Peng
Test Scheduling and Scan-Chain Division Under Power Constraint
Tenth Asian Test Symposium ATS 2001,2001, 2001.
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Erik Larsson, Zebo Peng and Gunnar Carlsson
The Design and Optimization of SOC Test Solutions
ICCAD-2001,2001, 2001.
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Erik Larsson and Zebo Peng
System-on-Chip Test Bus Design and Test Scheduling
International Test Synthesis Workshop,2000, 2000.
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Erik Larsson and Zebo Peng
A Technique for Test Infrastructure Design and Test Scheduling
Design and Diagnostic of Electronic Circuits and Systems Workshop DDECS 2000,2000, 2000.
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Ph.D. Theses
Ph.D., Lic. Theses
