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Complete Quadtree Based Construction of Bounding Volume Hierarchies for Ray Tracing

Ulises Olivares
Departament of Electrical Engineering Center for Research and Advanced Studies of the National Polytechnic Institute, Mexico

Arturo García
Intel Corporation, USA

Félix F. Ramos
Departament of Electrical Engineering Center for Research and Advanced Studies of the National Polytechnic Institute, Mexico

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Ingår i: Proceedings of SIGRAD 2015, June 1st and 2nd, Stockholm, Sweden

Linköping Electronic Conference Proceedings 120:4, s. 13-16

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Publicerad: 2015-11-24

ISBN: 978-91-7685-855-4

ISSN: 1650-3686 (tryckt), 1650-3740 (online)

Abstract

This paper presents an efficient space partitioning approach for building high quality Bounding Volume Hierarchies using x86 CPU architectures. Using this approach a structure can be built faster than a binned-SAH heuristic while the structure preserves its quality. This method consists of a hybrid implementation that uses binned-SAH for the top level and a binary partitioning approach for the rest of the levels. As a result, this method produces more regular axis-aligned bounding boxes (AABB) into a complete quadtree. Additionally, this approach takes advantage of the 4-wide vector units and exploits the SIMD extensions available for current CPU architectures. Using our construction approach a structure can be built up to three times faster than binned-SAH.

Nyckelord

Bounding volume hierarchies; quadtree based partitioning; ray-tracing

Referenser

[Cor14] CORPORATION I.: Getting the most from opencl 1.2: How to increase performance by minimizing buffer copies on intel processor graphics, 2014. 3

[DFM13] DOYLE M. J., FOWLER C., MANZKE M.: A hardware unit for fast sah-optimised bvh construction. ACM Trans. Graph. 32, 4 (July 2013), 139:1–139:10. 1

[GMOR14] GARCÍA A., MURGUIA S., OLIVARES U., RAMOS F. F.: Fast parallel construction of stack-less complete lbvh trees with efficient bit-trail traversal for ray tracing. In Proceedings of the 13th ACM SIGGRAPH International Conference on Virtual-Reality Continuum and Its Applications in Industry (New York, NY, USA, 2014), VRCAI ’14, ACM, pp. 151–158. 1, 2, 3

[HS86] HILLIS W. D., STEELE JR. G. L.: Data parallel algorithms. Commun. ACM 29, 12 (1986), 1170–1183. 3

[LGS*09] LAUTERBACH C., GARLAND M., SENGUPTA S., LUEBKE D., MANOCHA D.: Fast bvh construction on gpus. In In Proceedings of the EUROGRAPHICS â?AZ´09 (2009). 1

[NPP*11] NAH J.-H., PARK J.-S., PARK C., KIM J.-W., JUNG Y.-H., PARK W.-C., HAN T.-D.: T&iengine: Traversal and intersection engine for hardware accelerated ray tracing. In Proceedings of the 2011 SIGGRAPH Asia Conference (New York, NY, USA, 2011), SA ’11, ACM, pp. 160:1–160:10.

[PFL*13] PARKER S. G., FRIEDRICH H., LUEBKE D., MORLEY K., BIGLER J., HOBEROCK J., MCALLISTER D., ROBISON A., DIETRICH A., HUMPHREYS G., MCGUIRE M., STICH M.: Gpu ray tracing. Commun. ACM 56, 5 (May 2013), 93–101. 1

[SSK07] SHEVTSOV M., SOUPIKOV A., KAPUSTIN A.: Highly parallel fast kd-tree construction for interactive ray tracing of dynamic scenes. Comput. Graph. Forum 26, 3 (2007), 395–404. 1

[Wal07] WALD I.: On fast construction of sah-based bounding volume hierarchies. In Proceedings of the 2007 IEEE Symposium on Interactive Ray Tracing (Washington, DC, USA, 2007), RT ’07, IEEE Computer Society, pp. 33–40. 2

[Wal12] WALD I.: Fast construction of sah bvhs on the intel many integrated core (mic) architecture. IEEE Trans. Vis. Comput. Graph. (2012), 47–57. 1

[WIK*06] WALD I., IZE T., KENSLER A., KNOLL A., PARKER S. G.: Ray tracing animated scenes using coherent grid traversal. ACM Trans. Graph. 25, 3 (July 2006), 485–493. 1

[WWB*14] WALD I., WOOP S., BENTHIN C., JOHNSON G. S., ERNST M.: Embree: A kernel framework for efficient cpu ray tracing. ACM Trans. Graph. 33, 4 (July 2014), 143:1–143:8. 1, 3, 4

[ZHWG08] ZHOU K., HOU Q., WANG R., GUO B.: Real-time kd-tree construction on graphics hardware. ACM Trans. Graph. 27, 5 (Dec. 2008), 126:1–126:11. 1

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