Article | Proceedings of the 2nd Japanese Modelica Conference, Tokyo, Japan, May 17-18, 2018 | Semiconductor Package Thermal Impedance Extraction for Modelica Thermal Network Simulation Combined with VHDL-AMS model Linköping University Electronic Press Conference Proceedings
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Title:
Semiconductor Package Thermal Impedance Extraction for Modelica Thermal Network Simulation Combined with VHDL-AMS model
Author:
Eiji Nakamoto: ANSYS Japan K.K., Japan Kentaro Maeda: ANSYS Japan K.K., Japan Takayuki Sekisue: ANSYS Japan K.K., Japan
DOI:
10.3384/ecp1814886
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Full text (pdf)
Year:
2018
Conference:
Proceedings of the 2nd Japanese Modelica Conference, Tokyo, Japan, May 17-18, 2018
Issue:
148
Article no.:
012
Pages:
86-90
No. of pages:
5
Publication type:
Abstract and Fulltext
Published:
2019-02-21
ISBN:
978-91-7685-266-8
Series:
Linköping Electronic Conference Proceedings
ISSN (print):
1650-3686
ISSN (online):
1650-3740
Publisher:
Linköping University Electronic Press, Linköpings universitet


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Because of the emerging market demand for higher power with higher efficiency for the power semiconductor devices, thermal design of the semiconductor package and its cooling method has become one of the key elements for the power supply systems in power electric design. Thus, many thermal designers now require the junction-to-case thermal Impedance Z?JC since it is one of the most important thermal characteristics of semiconductor devices and thus, in November 2010, the more reliable and sufficiently reproducible measurement method without a case temperature measurement has been standardized by JEDEC as JESD 51-14 (https://www.jedec.org/standards-documents/docs/jesd51-14-0)

This paper shows the new feature in ANSYS simulation tool, ANSYS Electronics Desktop, which extracts Z?JC from JESD 51-14 compliant measurement data. The extracted Z?JC , or its cumulative expression of thermal resistance S(????h??)????=1 and capacitanceS(????h??)????=1 called “structure function”, is transformed to the Modelica thermal ladder network model. This Modelica model was simulated by ANSYS TwinBuilder, Multi-domain system simulator, and the junction temperature is reproduced by this simulation, that agreed well with the original measured temperature data. Further, Z?JC is split into two components, Junction-to-Die part(IC package DUT) and Heat-sink part(cold plate) in accordance with the guideline of Transient Dual Interface Measurement Procedure principle described in JESD 51-14. Then, Z?JC corresponding to IC package structure part is transformed to the VHDL-AMS model ( as IC Package thermal compact model ) while Heat-sink structure part is transformed to Modelica model(as testing fixture structure model). Those models built by two well-known physical model description languages were connected with the acausal (i.e., conservative) condition in ANSYS TwinBuilder and the thermal response of the combined model is evaluated. The result of the simulation matches to the full Junction-to-Heat-sink Modelica thermal ladder network model, that ensures Modelica and VHDL-AMS models can be connected in a single physical multi-domain system simulation environment in ANSYS TwinBuilder under the energy conservative principle, that might expand the potential applicability and the coverage for Modelica simulation for the broader application area.

Please send an email to eiji.nakamoto@ansys.com if there are any questions or suggestions regarding this paper.



Keywords: IC Package transient dual interface (TDI) measurement, IC Package Thermal Impedance, Structure Function, VHDL-AMS, Acausal Connection

Proceedings of the 2nd Japanese Modelica Conference, Tokyo, Japan, May 17-18, 2018

Author:
Eiji Nakamoto, Kentaro Maeda, Takayuki Sekisue
Title:
Semiconductor Package Thermal Impedance Extraction for Modelica Thermal Network Simulation Combined with VHDL-AMS model
DOI:
http://dx.doi.org/10.3384/ecp1814886
References:

1. D. Schweitzer, Software TDIM-MASTER: Program for the evaluation of transient dual interface measurements of Rth- JC. This software serves as reference and example implementation of the algorithms described in this standard and can be downloaded from the JEDEC homepage: http://www.jedec.org.

2. JEDEC JESD51-14, “Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction-to-Case of Semiconductor Devices with Heat Flow Through a Single Path”, 2010

Proceedings of the 2nd Japanese Modelica Conference, Tokyo, Japan, May 17-18, 2018

Author:
Eiji Nakamoto, Kentaro Maeda, Takayuki Sekisue
Title:
Semiconductor Package Thermal Impedance Extraction for Modelica Thermal Network Simulation Combined with VHDL-AMS model
DOI:
https://doi.org10.3384/ecp1814886
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