Article | Proceedings of The 9th EUROSIM Congress on Modelling and Simulation, EUROSIM 2016, The 57th SIMS Conference on Simulation and Modelling SIMS 2016 | Verifying an Implementation of Genetic Algorithm on FPGA-SoC using SystemVerilog Linköping University Electronic Press Conference Proceedings
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Title:
Verifying an Implementation of Genetic Algorithm on FPGA-SoC using SystemVerilog
Author:
Hayder Al-Hakeem: Department of Electrical and Energy Engineering, University of Vaasa, Finland Suvi Karhu: Department of Electrical and Energy Engineering, University of Vaasa, Finland Jarmo T. Alander: Department of Electrical and Energy Engineering, University of Vaasa, Finland
DOI:
10.3384/ecp171421095
Download:
Full text (pdf)
Year:
2018
Conference:
Proceedings of The 9th EUROSIM Congress on Modelling and Simulation, EUROSIM 2016, The 57th SIMS Conference on Simulation and Modelling SIMS 2016
Issue:
142
Article no.:
161
Pages:
1095-1101
No. of pages:
7
Publication type:
Abstract and Fulltext
Published:
2018-12-19
ISBN:
978-91-7685-399-3
Series:
Linköping Electronic Conference Proceedings
ISSN (print):
1650-3686
ISSN (online):
1650-3740
Publisher:
Linköping University Electronic Press, Linköpings universitet


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In this paper we show how an ef?cient implementation of genetic algorithms can be done on Field Programmable Gate Array i.e. on programmable hardware using the latest hardware design language aiding veri?cation. A four-way number partitioning problem of 128 unsigned 16-bit integers is used as a test case of the implementation. However, other similar problems could be solved using the proposed approach. The design was implemented using a combination of reusable veri?ed intellectual property cores for arithmetic operations and VHDL to describe the genetic algorithm operators in register transfer level. The register transfer level components were veri?ed in ModelSim using SystemVerilog assertions and cover groups. Test results show signi?cant improvements in performance compared to C language implementation running on a core i-7 desktop computer.

Keywords: genetic algorithms, veri?cation, FPGA, System on Chip (SoC)

Proceedings of The 9th EUROSIM Congress on Modelling and Simulation, EUROSIM 2016, The 57th SIMS Conference on Simulation and Modelling SIMS 2016

Author:
Hayder Al-Hakeem, Suvi Karhu, Jarmo T. Alander
Title:
Verifying an Implementation of Genetic Algorithm on FPGA-SoC using SystemVerilog
DOI:
http://dx.doi.org/10.3384/ecp171421095
References:
No references available

Proceedings of The 9th EUROSIM Congress on Modelling and Simulation, EUROSIM 2016, The 57th SIMS Conference on Simulation and Modelling SIMS 2016

Author:
Hayder Al-Hakeem, Suvi Karhu, Jarmo T. Alander
Title:
Verifying an Implementation of Genetic Algorithm on FPGA-SoC using SystemVerilog
DOI:
https://doi.org10.3384/ecp171421095
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