Article | Proceedings of The 9th EUROSIM Congress on Modelling and Simulation, EUROSIM 2016, The 57th SIMS Conference on Simulation and Modelling SIMS 2016 | From Low-Cost High-Speed Channel Design, Simulation, to Rapid Time-to-Market Linköping University Electronic Press Conference Proceedings
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Title:
From Low-Cost High-Speed Channel Design, Simulation, to Rapid Time-to-Market
Author:
Nansen Chen: SV Div., Home Technology Development, MediaTek Inc., Taiwan Mizar Chang: CTE Div. II, Analog Design and Circuit Technology, MediaTek Inc., Taiwan
DOI:
10.3384/ecp17142770
Download:
Full text (pdf)
Year:
2018
Conference:
Proceedings of The 9th EUROSIM Congress on Modelling and Simulation, EUROSIM 2016, The 57th SIMS Conference on Simulation and Modelling SIMS 2016
Issue:
142
Article no.:
112
Pages:
770-775
No. of pages:
6
Publication type:
Abstract and Fulltext
Published:
2018-12-19
ISBN:
978-91-7685-399-3
Series:
Linköping Electronic Conference Proceedings
ISSN (print):
1650-3686
ISSN (online):
1650-3740
Publisher:
Linköping University Electronic Press, Linköpings universitet


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Leadframe packages are always adopted as the low-end devices. When the low-cost channel including the leadframe package and the two-layer PCB is required for high-speed digital signaling over 1 Gb/s, the iteration of full channel simulation and analysis with reliable EDA tools should be taken before the device is rolled out. Different channel designs were characterized in the frequency domain using the 3-D full-wave electromagnetic field solver to analyze the bottleneck of channel performance. Comparison of the full channel S-parameters, the channel with the proposed DDR3 memory controller package suffers less insertion loss. The chip-package-board co-simulations in the time-domain using the chip HSPICE netlists and full channel S-parameters for the DDR3 data accessing at 1.2, 1.4, and 1.6 Gb/s were taken and demonstrated that the channel including the proposed package design had larger timing and voltage margins, and less jitter, overshoot and undershoot, which all conform to JEDEC Standard. The waveform measurement also verified the same prediction that the DDR3 memory controller encapsulated in the modified E-pad LQFP package achieved no cost impact and enough timing margin up to 1458 Mb/s. The performance of mature leadframe packages can be promoted if the careful package designs are taken.

Keywords: DDR3, E-pad, LQFP, return path, S-parameters, jitter, eye diagram, JEDEC

Proceedings of The 9th EUROSIM Congress on Modelling and Simulation, EUROSIM 2016, The 57th SIMS Conference on Simulation and Modelling SIMS 2016

Author:
Nansen Chen, Mizar Chang
Title:
From Low-Cost High-Speed Channel Design, Simulation, to Rapid Time-to-Market
DOI:
http://dx.doi.org/10.3384/ecp17142770
References:
No references available

Proceedings of The 9th EUROSIM Congress on Modelling and Simulation, EUROSIM 2016, The 57th SIMS Conference on Simulation and Modelling SIMS 2016

Author:
Nansen Chen, Mizar Chang
Title:
From Low-Cost High-Speed Channel Design, Simulation, to Rapid Time-to-Market
DOI:
https://doi.org10.3384/ecp17142770
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