Article | GigaHertz 2003. Proceedings from the Seventh Symposium | A non-overlapping two-phase clock generator with adjustable duty cycle

Title:
A non-overlapping two-phase clock generator with adjustable duty cycle
Author:
Magnus Karlsson: University of Kalmar, Sweden Mark Vesterbacka: Linköping University, Sweden Wlodek Kulesza: University of Kalmar, Sweden
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Full text (pdf)
Year:
2003
Conference:
GigaHertz 2003. Proceedings from the Seventh Symposium
Issue:
008
Article no.:
028
No. of pages:
4
Publication type:
Poster
Published:
2003-11-06
Series:
Linköping Electronic Conference Proceedings
ISSN (print):
1650-3686
ISSN (online):
1650-3740
Publisher:
Linköping University Electronic Press; Linköpings universitet


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In this paper; a new robust non-overlapping twophase clock generator with adjustable duty cycle is proposed. The generator is based on a differential negative edge trigged D flip-flop and has small area and power consumption. The maximal clock rate and delay are also improved reaching a clock frequency of 1.0 GHz in a standard 0.35 µm CMOS process. The new clock generator is inherently glitch and spike free and robust against slow clock transitions; that reduces the design effort significantly.

GigaHertz 2003. Proceedings from the Seventh Symposium

Author:
Magnus Karlsson, Mark Vesterbacka, Wlodek Kulesza
Title:
A non-overlapping two-phase clock generator with adjustable duty cycle
References:

[1] J.P. Uyemura; Circuit Design for CMOS VLSI; Kluwer Academic Publisher; 1992.


[2] U. Sjöström; M. Karlsson; and M. Hörlin; “Designand Implementation of a Digital Down Converter Chip;” in Proc. of European Signal Processing Conference EUSIPCO’96; Vol. 1; pp. 284-287; Trieste; Italy; Sept.; 1996.


[3] M. Karlsson; and M. Vesterbacka; “A RobustNon-Overlapping Two-Phase Clock Generator;” in Proc. of Swedish System on Chip Conference SSoCC’03; Sundbyholms slott; Eskilstuna; Sweden; Mars 8-9; 2003.


[4] M. Karlsson; M. Vesterbacka; “Implementation of Bit-Serial Adders using Robust Differential Logic;” in Proc. IEEE Conf. NORCHIP’97. pp. 366-373; Tallin; Estonia; Nov.; 1997.


[5] J. Yuan; and C. Svensson; “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings;” IEEE J. of Solid-State Circuits; Vol. SC-32; No. 1. pp. 62-69; Jan.; 1997.


[6] M. Afghahi; “A Robust Single Phase Clocking forLow Power; High Speed VLSI Applications;” IEEE J. of Solid-State Circuits; Vol. SC-31; No. 2; pp. 247-254; Feb.; 1996.

GigaHertz 2003. Proceedings from the Seventh Symposium

Author:
Magnus Karlsson, Mark Vesterbacka, Wlodek Kulesza
Title:
A non-overlapping two-phase clock generator with adjustable duty cycle
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