Several passivation schemes on 4H-SiC MESFETs have been studied. Two main configurations are compared. MESFET structures with thin passivation layer or no passivation layer (Configuration 1) exhibit high breakdown voltage but also current instability after high voltage Vds stress. Thick SiO2 passivation covering the gate (Configuration 2) improves the current stability but yields lower breakdown voltage and higher gate leakage current. Surface trapping effects are considered as the main cause of the observed phenomena.