Publications for Peter Caputa
Co-author map based on ISI articles 2007-

Keywords

wire vlsi skew scheme power on-chip model lna latency interconnects interconnect global energy dissipation delay cmos clock chip buses bus

Journal Articles

Peter Caputa and Christer Svensson
  Well-Behaved Global On-Chip Interconnect
  IEEE Transactions on Circuits and Systems I: Regular Papers, 2005, 52(2), 318-323.
 Web of Science® Times Cited: 4

Chapters in Books

Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Andersson, Atila Alvandpour and Christer Svensson
  An extended transition energy cost model for buses in deep submicron technologies
  Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004. Proceedings, Springer Berlin/Heidelberg, 2004, 849-858.


Conference Articles

Peter Caputa and Christer Svensson
  An On-Chip Delay- and Skew-Insensitive Multi-Cycle Comunication Scheme
  International Solid-State Circuits Conference 2006, San Fransisco, USA, 2006.


Peter Caputa and Christer Svensson
  A 3 Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency
  Proceedings of the International Conference on VLSI Design 2006, Hyderabad, India, 2006.


Peter Caputa and Christer Svensson
  A 3Gb/s/wire, 5mm Long, Low Latency, Global On-Chip Bus in 0.18µm CMOS.
  SSoCC 2005,2005, 2005.


Rebecca Källsten, Peter Caputa and Christer Svensson
  Capacitive Crosstalk Effects on On-Chip Interconnect Latencies and Data-Rates
  Proceedings of the 23rd Norchip Conference, Oulu, Finland, 2005.


Peter Caputa, Atila Alvandpour and Christer Svensson
  High-Speed On-Chip Interconnect Modeling for Circuit Simulation
  Proceedings of the Norchip Conference, Oslo, Norway, November, 2004.


Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Andersson, Atila Alvandpour and Christer Svensson
  An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
  Proceedings of the Power and Timing Modeling, Optimization and Simulation Conference, Santorini, Greece, 2004.


 Web of Science® Times Cited: 1

Peter Caputa, Mark A. Anders, Christer Svensson, Ram K. Krishnamurthy and Shekhar Borkar
  A Low-swing Single-ended L1 Cache Bus Technique for Sub-90 nm Technologies
  Proceedings of the European Solid-State Circuits Conference, Leuven, Belgium, 2004.


Christer Svensson and Peter Caputa
  High Bandwidth, Low-Latency Global Interconnect
  VLSI Circuits and Systems, Proceedings of the SPIE, Vol. 5117, Gran Canaria, Spain, May, 2003.


Peter Caputa and Christer Svensson
  Low power, low latency global interconnect.
  Swedish System-on-Chip,2002, 2002.


Christer Svensson, Peter Caputa and Stefan Andersson
  A tuned, inductorless, recursive filter LNA in CMOS.
  RVK 02 conference.,2002, 2002.


Stefan Andersson, Peter Caputa and Christer Svensson
  A Tuned, Inductorless, Recursive Filter LNA in CMOS
  Proceedings of the European Solid-State Circuit Conference (ESSCIRC), Florens, Italy, September, 2002.


Peter Caputa and Christer Svensson
  Low-Power, Low-Latency Global Interconnect
  Proceedings of the IEEE ASIC/SOC Conference, Rochester, USA, 2002.


Ph.D. Theses

Peter Caputa
  Efficient high-speed on-chip global interconnects
  2006.


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