Publications for Henrik Eriksson

Publications for Henrik ErikssonCo-author map based on ISI articles 2007-

Conference Articles

Henrik Eriksson, Tomas Henriksson and Per Larsson-Edefors
  Full-custom vs standard-cell based design - An adder comparison.
  Swedish System-on-Chip conference.,2002, 2002.


Per Larsson-Edefors, Henrik Eriksson, Daniel Eckerbert and Atila Alvandpour
  Low-Power Design of Delay-Constrained Circuits Using Dual-VT Process Technology
  In proceedings of: International Worskshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 2001.


Henrik Eriksson, Per Larsson-Edefors and W.P. Marnane
  A regular parallel multiplier which utilizes multiple carry-propagate adders.
  IEEE International Symposium on Circuits and Systems ISCAS.,2001, 2001.


Henrik Eriksson, Per Larsson-Edefors and Atila Alvandpour
  A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.
  IEEE International Symposium on Circuits and Systems ISCAS.,2001, 2001.


Tomas Henriksson, Henrik Eriksson, Ulf Nordqvist, Per Larsson-Edefors and Dake Liu
  VLSI Implementation of CRC-32 for 10 Gigabit Ethernet
  The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001: ICECS 2001, 2001.