Publications for Henrik Eriksson
Co-author map based on ISI articles 2007-
Conference Articles
Henrik Eriksson, Tomas Henriksson and Per Larsson-Edefors
Full-custom vs standard-cell based design - An adder comparison.
Swedish System-on-Chip conference.,2002, 2002.
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Per Larsson-Edefors, Henrik Eriksson, Daniel Eckerbert and Atila Alvandpour
Low-Power Design of Delay-Constrained Circuits Using Dual-VT Process Technology
In proceedings of: International Worskshop on Power and Timing Modeling, Optimization and Simulation, PATMOS, 2001.
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Henrik Eriksson, Per Larsson-Edefors and W.P. Marnane
A regular parallel multiplier which utilizes multiple carry-propagate adders.
IEEE International Symposium on Circuits and Systems ISCAS.,2001, 2001.
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Henrik Eriksson, Per Larsson-Edefors and Atila Alvandpour
A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.
IEEE International Symposium on Circuits and Systems ISCAS.,2001, 2001.
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Ph.D., Lic. Theses
