Publications for Breeta Sengupta
Co-author map based on ISI articles 2007-
Journal Articles
Conference Articles
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
VLSI 2012, 2012.
|
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Planning for Core-based 3D Stacked ICs under Power Constraints
RASDAT 2012, 2012.
|
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Planning for 3D Stacked ICs with Through-Silicon Vias
3D-TEST, 2011.
|
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Scheduling for 3D Stacked ICs under Power Constraints
2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT), Chennai, India, January 6-7, 2011, 2011.
|
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Scheduling Tests for 3D Stacked Chips under Power Constraints
Sixth IEEE International Symposium on Electronic Design, Test and Application (DELTA), 2011, Queenstown, NZ, 2011.
|
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
<em>The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011</em>, 2011.
|
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias (poster)
<em>European Test Symposium (ETS11), Trondheim, Norway, May 23-27, 2011.</em>, 2011.
|
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Power Constrained Test Scheduling for 3D Stacked Chips: (poster)
<em>1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA.</em>, 2010.
|
Breeta SenGupta, Urban Ingelsson and Erik Larsson
Scheduling Tests for Stacked 3D Chips under Power Constraints
<em>Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed)</em>, 2010.
|
Ph.D., Lic. Theses
