Publications for Andreas Ehliar
Co-author map based on ISI articles 2007-

Keywords

xilinx virtex-4 optimized multiplier mhz fpgas fpga floating-point floating fixed dsp devices designs decoding chip backend asic arithmetics architecture 16-bit

Journal Articles

Mikael Gustavsson, Farooq Ul Amin, Anders Bjorklid, Andreas Ehliar, Cheng Xu and Christer Svensson
  A High-Rate Energy-Resolving Photon-Counting ASIC for Spectral Computed Tomography
  IEEE Transactions on Nuclear Science, 2012, 59(1), 30-39.
   Fulltext  PDF  
 Web of Science® Times Cited: 5

Per Karlström, Andreas Ehliar and Dake Liu
  High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
  IET Computers and digital techniques, 2008, 2, 305-313.
 Web of Science® Times Cited: 4

Conference Articles

Oscar Gustafsson and Andreas Ehliar
  Low-complexity general FIR filters based on Winograd's inner product algorithm
  IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China, 2013.


Andreas Ehliar
  EBRAM - Extending the BlockRAMs in FPGAs to support caches and hash tables inan efficient manner
  IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, April 29 - May 1 2012, Toronto, ON, Canada, 2012.


Andreas Ehliar and Jacob Siverskog
  Using Partial Reconfigurability to aid Debugging of FPGA Designs
  VII Southern Conference on Programmable Logic (SPL), 2011.


Andreas Ehliar
  Optimizing Xilinx designs through primitive instantiation
  FPGAworld '10 Proceedings of the 7th FPGAworld Conference, 2010.


Andreas Ehliar and Dake Liu
  An Asic Perspective on FPGA Optimizations
  19th International Conference on Field Programmable Logic and Applications (FPL), 2009.


 Web of Science® Times Cited: 1

Andreas Ehliar and Dake Liu
  An ASIC Perspective on High Performance FPGA Design
  , 2009.


Andreas Ehliar, Per Karlström and Dake Liu
  A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
  International Conference on Field Programmable Logic and Applications FLP 2008, Heidelberg, Germany, 2008, 2008.


 Web of Science® Times Cited: 1

Andreas Ehliar, Johan Eilert and Dake Liu
  A Comparison of Three FPGA Optimized NoC Architectures
  Swedish System-on-Chip Conference, SSoCC,2007, 2007.


Andreas Ehliar and Dake Liu
  Thinking outside the flow: Creating customized backend tools for Xilinx based designs
  4th annual FPGAworld Conference, Stockholm, 2007, 2007.


Andreas Ehliar and Dake Liu
  An FPGA based Open Source Network-on-chip Architecture
  17th International Conference on Fileld Programmable Logic and Applications, FPL, Amsterdam, Holland, 2007, 2007.


Per Karlström, Andreas Ehliar and Dake Liu
  High Performance, Low Latency FPGA based Floating Point Adder and Multiplier Units in a Virtex 4
  NORCHIP 2006: The Nordic Microelectronics Event. 2006, 2006.


Andreas Ehliar and Dake Liu
  A Network on Chip based gigabit Ethernet router implemented on an FPGA
  SSoCC Swedish System-on-Chip Conference,2006, 2006.


Di Wu, Per Karlström, Johan Eilert, Andreas Ehliar and Dake Liu
  Media DSP: An Application Specific Heterogeneous Multiprocessor SoC
  SSoCC Swedish System-on-Chip Conference,2006, 2006.


Andreas Ehliar and Dake Liu
  Flexible Route Lookup Using Range Search
  The Third IASTED International Conference on Communications and Computer Networks,2005, 2005.


Daniel Wiklund, Andreas Ehliar and Dake Liu
  Design of an internet core router using the SoCBUS network on chip
  International Symposium on Signals, Circuits, and Systems ISSCS,2005, 2005.


Andreas Ehliar, Daniel Wiklund and Dake Liu
  Feasibility study of a core router based on a network on chip
  Swedish System on Chip Conference SSoCC,2005, 2005.


Johan Eilert and Andreas Ehliar
  Design of a Floating Point DSP for Full Precision MPEG-I Layer II and III Decoding
  Swedish System on Cihip Conference SSoCC,2005, 2005.


Andreas Ehliar and Dake Liu
  Benchmarking network processors
  Swedish System-on-Chip Conference,2004, 2004.


Mikael Olausson, Andreas Ehliar, Johan Eilert and Dake Liu
  Reduced floating point for MPEG1/2 layer III decoding
  IEEE International Conference on Acoustics, Speech, and Signal Processing, 2004. Proceedings. (ICASSP '04)., 2004.


Johan Eilert, Andreas Ehliar and Dake Liu
  Using low precision floating point numbers to reduce memory cost for MP3 decoding
  International Workshop on Multimedia Signal Processing, 2004.


Ph.D. Theses

Jian Wang
  Low Overhead Memory Subsystem Design for a Multicore Parallel DSP Processor
  2014.


  Fulltext PDF

Andreas Ehliar
  Performance driven FPGA design with an ASIC perspective
  2009.


  Fulltext PDF

Licentiate Theses

Aspects of system-on-chip design for FPGAs
  2008.