Publications for Andreas Ehliar
Co-author map based on ISI articles 2007-
Journal Articles
Andreas Ehliar
EBRAM - Extending the BlockRAMs in FPGAs to support caches and hash tables inan efficient manner
Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012, 2012, , 242-242.
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Mikael Gustavsson, Farooq Ul Amin, Anders Bjorklid, Andreas Ehliar, Cheng Xu and Christer Svensson
A High-Rate Energy-Resolving Photon-Counting ASIC for Spectral Computed Tomography
IEEE Transactions on Nuclear Science, 2012, 59(1), 30-39.
Fulltext  Web of Science® Times Cited: 2 |
Per Karlström, Andreas Ehliar and Dake Liu
High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
IET Computers and digital techniques, 2008, 2, 305-313.
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Conference Articles
Oscar Gustafsson and Andreas Ehliar
Low-complexity general FIR filters based on Winograd's inner product algorithm
IEEE International Symposium on Circuits and Systems (ISCAS 2013), 19-23 May 2013, Beijing, China, 2013.
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Andreas Ehliar and Jacob Siverskog
Using Partial Reconfigurability to aid Debugging of FPGA Designs
VII Southern Conference on Programmable Logic (SPL), 2011.
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Andreas Ehliar
Optimizing Xilinx designs through primitive instantiation
FPGAworld '10 Proceedings of the 7th FPGAworld Conference, 2010.
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Andreas Ehliar and Dake Liu
An Asic Perspective on FPGA Optimizations
19th International Conference on Field Programmable Logic and Applications (FPL), 2009.
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Andreas Ehliar and Dake Liu
An ASIC Perspective on High Performance FPGA Design
, 2009.
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Andreas Ehliar, Per Karlström and Dake Liu
A High Performance Microprocessor with DSP Extensions Optimized for the Virtex-4 FPGA
International Conference on Field Programmable Logic and Applications FLP 2008, Heidelberg, Germany, 2008, 2008.
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Andreas Ehliar, Johan Eilert and Dake Liu
A Comparison of Three FPGA Optimized NoC Architectures
Swedish System-on-Chip Conference, SSoCC,2007, 2007.
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Andreas Ehliar and Dake Liu
Thinking outside the flow: Creating customized backend tools for Xilinx based designs
4th annual FPGAworld Conference, Stockholm, 2007, 2007.
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Andreas Ehliar and Dake Liu
An FPGA based Open Source Network-on-chip Architecture
17th International Conference on Fileld Programmable Logic and Applications, FPL, Amsterdam, Holland, 2007, 2007.
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Andreas Ehliar and Dake Liu
A Network on Chip based gigabit Ethernet router implemented on an FPGA
SSoCC Swedish System-on-Chip Conference,2006, 2006.
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Di Wu, Per Karlström, Johan Eilert, Andreas Ehliar and Dake Liu
Media DSP: An Application Specific Heterogeneous Multiprocessor SoC
SSoCC Swedish System-on-Chip Conference,2006, 2006.
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Andreas Ehliar and Dake Liu
Flexible Route Lookup Using Range Search
The Third IASTED International Conference on Communications and Computer Networks,2005, 2005.
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Daniel Wiklund, Andreas Ehliar and Dake Liu
Design of an internet core router using the SoCBUS network on chip
International Symposium on Signals, Circuits, and Systems ISSCS,2005, 2005.
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Andreas Ehliar, Daniel Wiklund and Dake Liu
Feasibility study of a core router based on a network on chip
Swedish System on Chip Conference SSoCC,2005, 2005.
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Johan Eilert and Andreas Ehliar
Design of a Floating Point DSP for Full Precision MPEG-I Layer II and III Decoding
Swedish System on Cihip Conference SSoCC,2005, 2005.
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Andreas Ehliar and Dake Liu
Benchmarking network processors
Swedish System-on-Chip Conference,2004, 2004.
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Mikael Olausson, Andreas Ehliar, Johan Eilert and Dake Liu
Reduced floating point for MPEG 1/2 Layer III decoding
International Conference on acoustics, speech and signal processing, ICASSP,2004, 2004.
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Johan Eilert, Andreas Ehliar and Dake Liu
Using low precision floating point numbers to reduce memory cost for MP3 decoding
International Workshop on Multimedia Signal Processing, 2004.
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Ph.D. Theses
Licentiate Theses
Ph.D., Lic. Theses
